This invention relates to data transmission systems, and more particularly to phase-synchronizing or phase-aligning a received data signal with a received reference clock signal.
Some data transmission systems send one or more serial data streams in parallel with a reference clock signal. For ease of reference it will generally be assumed herein that there is one data stream in parallel with the reference clock signal, but those skilled in the art will appreciate that any number of data streams can be sent in parallel with the reference clock signal. The transmitter in such systems generally outputs the data stream and the reference clock signal in phase and frequency synchronism with one another. However, phase synchronism may be lost by the time these signals reach the receiver. This may be due to any number of reasons, such as slightly different transmission characteristics of the transmission paths for the two signals from the transmitter to the receiver.
The receiver typically needs to use the reference clock signal to capture the data in the data signal. If the reference clock signal is not received by the receiver in phase synchronization with the data signal, the reference clock signal cannot be reliably used to capture the received data signal. For example, some of the data may be misinterpreted and data errors may result. The specifications of some signalling systems may require that the received data signal be clocked very near the center of the “eye” of the unit interval of the data signal to help ensure zero or acceptably low data error rates. (The unit interval (“UI”) is the duration of any one bit in the data signal.) For example, such signalling systems may have relatively loose specifications regarding data signal jitter and/or communication path quality, so that clocking the received data very near the center of the unit interval eye is especially important for correct interpretation of the received data.